1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit, and more particularly, to a method of fabricating a load resistor in a static random access memory (SRAM).
2. Description of the Related Art
A SRAM is a very widely used device in integrated circuit, especially in information electronic products. To fabricate a device a small dimension and a high integration is now a leading trend in manufacture. A load resistor is one of the devices comprised by a SRAM cell. Typically, the load resistor is formed of a lightly doped or undoped polysilicon section.
A circuit diagram of a SRAM cell is shown in FIG. 1. The SRAM cell comprises two load resistors R.sub.1, R.sub.2, two pull down transistors Q.sub.1, Q.sub.2, and two pass transistors Q.sub.3, Q.sub.4. A first polisilicon layer is employed as a gate of the transistor Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4, and a second polysilicon is formed for load resistor. The second polysilicon layer comprises a high resistant part used as a load resistor, and a low resistant part used as an interconnect. In the prior art technique, the low resistant part, that is, the interconnect, is formed by heavily doping a part of the second polysilicon layer, while the high resistant part, that is, the load resistor, is formed by a lightly doped or undoped part of the second polysilicon layer. The interconnect and the load resistor construct a circuit path from the power source V.sub.cc to the nodes A and B. As mentioned above, the interconnect and the load resistors are both formed by the second polysilicon layer. The thickness of the interconnect and the load resistors are thus the same.
A conventional method for forming a load resistor of a SRAM is described as follows with reference to FIG. 2A to FIG. 2J.
In FIG. 2A, a silicon substrate 10 is provided. A transistor comprising a gate oxide layer 13, a gate 12, a source/drain region 14 and 16 and a field oxide layer 11 are formed on the substrate 10. A dielectric layer 18 is formed over the substrate 10.
In FIG. 2B, a photo-resist layer 20 with an opening exposing a part of the dielectric layer 18 over the source/drain region 14 and 16 and the gate 12 is formed.
In FIG. 2C, the exposed part of the dielectric layer 18 is removed to form vias to expose the source/drain region 14 and 16 and the gate 12.
In FIG. 2D, the photo-resist layer 20 is removed. A polysilicon layer 22 is formed. According to a prior art technique, the polysilicon layer 22 is lightly doped with dopant, or alternatively, the polysilicon layer 22 is undoped.
In FIG. 2E, a photo-resist layer 24 is formed with openings which expose portions of the polysilicon layer 22.
In FIG. 2F, the exposed polysilicon layer 22 is removed to leave an open circuit between the source/drain regions 14, 16 and the gate 12. The photo-resist layer 24 is then removed as shown in FIG. 2G.
In FIG. 2H, a photo-resist layer 26 is formed to cover portions of the polysilicon layer 22. The covered portions of the polysilicon layer 22 are to be formed as load resistors, whereas the exposed portions of the polysilicon layer 22 are to be formed as interconnects. In FIG. 2I, the exposed portions of the polysilicon layer 22 are heavily doped to reduce the resistance thereof. Thus, the interconnects comprise the conducting component 28 of V.sub.cc, the conductive component 30 of the drain region, the conductive component 36 of the source region, and the conductive component 32 of the gate.
In FIG. 2J, the photo-resist layer 26 is removed to expose the portions of the polysilicon layer 22 as load resistors denoted as 34, 38.
In the above fabrication method for forming load resistors in a SRAM, a polysilicon layer is formed for fabricating both load resistors and interconnects. The load resistors are formed without or with light doping, while the interconnects are formed by heavily doping. As mentioned above, the load resistors are formed with the same thickness as the interconnects. As the integration increases, to form a load resistor with a sufficiently high resistance, the load resistor is commonly formed with a reduced thickness. Consequently, the thickness of the interconnects is reduced to affect the conductivity thereof.
Moreover, in the above method, the interconnects are formed by heavily doping. The heavily doped ions in the interconnects easily diffuse out of the range of the interconnect to the load resistor. The effective length of the load resistor is thus reduced and causes a reduced resistance, and therefore, affects the quality of the device.
Another method to increase the resistance of the load resistor is to increase the width. However, as the integration grows higher and higher the ability to increase the width is very restricted.